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计算机工程

• 体系结构与软件技术 • 上一篇    下一篇

基于统计分析的指令高速缓存优化技术

陈 辰,黄 凯,王钰博,严晓浪   

  1. (浙江大学超大规模集成电路设计研究所,杭州310027)
  • 收稿日期:2013-11-25 出版日期:2014-10-15 发布日期:2014-10-13
  • 作者简介:陈 辰(1988 - ),男,硕士研究生,主研方向:数字集成电路设计,缓存优化;黄 凯,副教授、博士;王钰博,硕士研究生; 严晓浪,教授。

Instruction High-speed Cache Optimization Techniques Based on Statistic Analysis

CHEN Chen,HUANG Kai,WANG Yu-bo,YAN Xiao-lang   

  1. (Institute of VLSI Design,Zhejiang University,Hangzhou 310027,China)
  • Received:2013-11-25 Online:2014-10-15 Published:2014-10-13

摘要: 针对现有高速缓存技术计算方法复杂、适用性差的问题,提出基于统计分析的指令高速缓存优化技术。采用GUN 覆盖率分析工具和性能分析工具对代码进行静态分析,降低优化过程中的计算复杂度。在软件代码方面,通过优化的缓存块着色算法、地址段静态锁定、代码段选择性不缓存等技术,提高指令高速缓存的读取效率。给出缓存锁定选择排序公式,用于判断代码段是否锁定或不缓存,有效增加指令高速缓存的利用效率。实验结果表明,该优化技术能使程序执行时间平均减少8% ,缓存命中率平均提高23% 。

关键词: 高速缓存, 优化的缓存块着色算法, 过程排序, 缓存锁定, 选择性不缓存, 缓存锁定选择排序

Abstract: Aiming at the problem that existing cache technology has computational complexity and poor applicability, instruction cache optimization techniques based on statistic analysis by using GNU coverage analysis tool and performance analysis tools are proposed. It uses optimization techniques,including optimized cache line coloring algorithm,static use of cache locking and code selectively non-caching,can significantly improve the efficiency of instruction cache reading. Also a Cache Locking Selection Sorting(CLSS) is proposed to evaluate the code segment which can be locked or noncached. Simulations show that these techniques make the program running time reduced by 8% ,and make the cache hit rate increased by 23% .

Key words: high-speed cache, optimized cache block coloring algorithm, process sorting, cache locking, selective no cache, Cache Locking Selection Sorting(CLSS)

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