计算机工程

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一种基于FPGA的并行H.264/AVC编码器架构

张建国  1,关则昂  1,徐渊  2,刘劲松  2   

  1. (1.深圳市振华微电子有限公司,广东 深圳 518060; 2.深圳大学信息工程学院,广东 深圳 518060)
  • 收稿日期:2014-10-15 出版日期:2015-12-15 发布日期:2015-12-15
  • 作者简介:张建国(1961-),男,工程师,主研方向:电子通信,图像处理;关则昂,硕士;徐渊,讲师、博士;刘劲松,硕士。

A Parallel H.264/AVC Encoder Architecture Based on FPGA

ZHANG Jianguo  1,GUAN Zeang  1,XU Yuan  2,LIU Jingsong  2   

  1. (1.Shenzhen Zhenhua Microelectronics Co.,Ltd.,Shenzhen 518060,China; 2.School of Information Engineering,Shenzhen University,Shenzhen 518060,China)
  • Received:2014-10-15 Online:2015-12-15 Published:2015-12-15

摘要: 为了提高视频在高性能压缩效率和实时编码方面的性能,提出一种新型的并行处理架构。采用现场可编程门阵列(FPGA)实现整个H.264编码系统设计,包括帧内和帧间预测、变换编码等全部编码过程。针对FPGA的低频工作特点采用高度流水线设计、双缓存机制以及多时域工 作等优化处理模式,设计一种快速的宏块匹配预测架构,将图像分辨率设置成可调参数,在Xilinx公司的Virtex-6芯片上应用该硬件系统。测试结果证明,该IP系统在保持较好压缩性能的基础上720P的帧率可达每秒34帧。

关键词: 视频编码器, H.264编码, 帧内预测, 帧间预测, 现场可编程门阵列, 运动估计

Abstract: To deal with the high performance video compression efficiency and real-time playback solutions,a H.264/AVC encoder IP core based on Field Programmable Gate Array(FPGA) is implemented,which contains all the coding process,including both intra and inter prediction,transform-based coding, etc.,and a new type of parallel processing architecture is proposed.To compensate the low-frequency of FPGA chip,high degree of pipeline structure,double-buffers and multi-time-domain are used.Moreover,it also proposes a fast macro-block-matching predicted architecture,and the video resolution is configurable.The encoder is implemented on the Xilinx Virtex-6 chip,results show that the encoder is able to reach 720P 34 frames per second with a good compression.

Key words: video encoder, H.264 encoding, intra prediction, inter prediction, Field Programmable Gate Array(FPGA), motion estimation

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