检索
E-mail
RSS
作者投稿和查稿 主编审稿 专家审稿 编委审稿 远程编辑

计算机工程 ›› 2012, Vol. 38 ›› Issue (16): 35-39.doi: 10.3969/j.issn.1000-3428.2012.16.009

• 专栏 • 上一篇    下一篇

基于异构多核处理器的H.264并行编码算法

吕明洲，陈耀武   

  1. (浙江大学数字技术及仪器研究所，杭州 310027)
  • 收稿日期:2011-11-18 修回日期:2011-12-21 出版日期:2012-08-20 发布日期:2012-08-17
  • 作者简介:吕明洲(1986－)，男，硕士研究生，主研方向：视频编解码，嵌入式系统；陈耀武，教授、博士生导师
  • 基金项目:

    国家自然科学基金资助项目(40927001)；国家科技支撑计划基金资助项目(2009BAF39B03)；浙江省级重点科技创新团队基金资助项目(2011R09021-06)

H.264 Parallel Coding Algorithm Based on Heterogeneous Multi-core Processor

LV Ming-zhou, CHEN Yao-wu   

  1. (Institute of Advanced Digital Technology and Instrument, Zhejiang University, Hangzhou 310027, China)
  • Received:2011-11-18 Revised:2011-12-21 Online:2012-08-20 Published:2012-08-17

PDF

1159

被引次数

25 | 1

摘要：

H.264视频编码标准计算复杂度较高，难以完成高清视频的实时编码。为此，提出异构多核DM6467平台的H.264并行编码算法。综合DM6467内部各个硬件加速引擎的依赖关系和存储器特点，设计宏块级并行编码算法，通过分析多slice模式流水线的特点，以及数字信号处理器和ARM双核任务分配，提出合并流水线、核间负载均衡的优化方案。实验结果表明，优化后的编码器效率提高18%，能实现在DM6467平台上1080P的实时编码。

关键词: H.264编码器, 多核, DM6467平台, HDVICP加速引擎, 并行算法, 流水线

Abstract:

H.264 video coding standard has high computing complexity, and is difficult to meet the high-definition video in real-time encoding. In order to solve this problem, this paper proposes a parallel coding algorithm on heterogeneous multi-core platform DM6467. By analyzing the dependence between different hardware accelerators and the characteristics of different levels of memory, a macroblock level parallel scheme is designed. Further optimization is carried out by merging the pipeline of adjacent slices and balancing the tasks assigned to Digital Signal Processor (DSP) and ARM cores. Experimental result shows that the efficiency is improved by 18%, and 1080P real-time H.264 video encoder can be realized on DM6467 platform.

Key words: H.264 encoder, multi-core, DM6467 platform, HDVICP accelerating engine, parallel algorithm, pipeline

中图分类号: