基于UVM的SoC环境中PCIe验证平台设计

doi:10.19678/j.issn.1000-3428.0068240

摘要/Abstract

摘要：

系统级芯片(SoC)集成多种外设接口, 其外设接口的验证工作已经成为芯片开发最耗时的环节之一。PCIe协议为系统内部提供了高速的点对点串行互联服务, 同时还支持热插拔和热交换, 逐渐成为一种通用的总线协议。使用传统硬件描述语言(HDL)对PCIe接口设计进行验证时, 存在短时间内难以覆盖多种设计场景和边界条件, 以及验证不完备等问题。为了解决上述问题, 利用统一验证方法学(UVM)搭建1个PCIe接口的验证平台。该平台采用UVM定义的框架和测试类, 实现了顶层环境集成和测试约束的设计, 具有可重用性强和验证全面的特点。实现的内容包括SoC系统级环境集成、待测模块设计与连接、验证平台中sequencer类和monitor类的实现, 以及部分接口设计。为了确保测试用例覆盖尽可能多地设计状态和路径, 针对性地划分不同功能点, 并设计约束条件。通过多种覆盖率指标对测试用例的有效性和覆盖程度进行评估。实验结果表明, 该验证平台能缩短验证周期, 使综合覆盖率提高30%以上。

关键词: PCIe协议, 验证平台, 统一验证方法学, 覆盖率, 验证IP

Abstract:

The System of Chip (SoC) integrates multiple peripheral interfaces, the verification of which has become one of the most time-consuming steps in chip development. The PCIe protocol provides high-speed peer-to-peer serial interconnection services within the system, while supporting hot swapping, which has gradually become a universal bus protocol. When using conventional Hardware Description Languages (HDL) to validate PCIe interface designs, problems usually arise, such as difficulty in covering multiple design scenarios and boundary conditions in a short period, leading to insufficient verification. To address the above issues, this study utilizes Universal Verification Methodology (UVM) to build a PCIe interface validation platform. This platform adopts a UVM-defined framework and test classes, achieving top-level environmental integration and design of test constraints, with strong reusability and comprehensive verification. This implementation includes SoC system-level environmental integration, design, and connection of the modules to be tested, implementation of sequencer and monitor classes in the verification platform, and partial interface design. To ensure that the test cases cover as many design states and paths as possible, different functional points are divided deliberately, and constraint conditions are designed to evaluate the effectiveness and coverage of test cases using various coverage indicators. The experimental results show that the verification platform can curtail the verification cycle and increase the comprehensive coverage by more than 30%.

Key words: PCIe protocol, verification platform, Universal Verification Methodology(UVM), coverage rate, verification IP

高秋辰, 胡勇华. 基于UVM的SoC环境中PCIe验证平台设计[J]. 计算机工程, 2024, 50(9): 189-196.

GAO Qiuchen, HU Yonghua. Design of PCIe Verification Platform in SoC Environment Based on UVM[J]. Computer Engineering, 2024, 50(9): 189-196.

https://www.ecice06.com/CN/Y2024/V50/I9/189

图/表 10

图1 p_sequencer类结构

Fig.1 Structure of p_sequencer class

图2 随机约束域与功能覆盖率关系

Fig.2 The relationship between random constraint domain and functional coverage

图3 PCIe协议结构层次图

Fig.3 Hierarchy diagram of PCIe protocol structure

图4 SoC与VIP实例连接示意图

Fig.4 Schematic diagram of connecting the SoC to the VIP instance

图5 仿真实验波形示意图

Fig.5 Schematic diagram of simulation experiment waveform

参考文献 27

1	LI A, SONG S L, CHEN J Y, et al. Evaluating modern GPU interconnect: PCIe, NVLink, NV-SLI, NVSwitch and GPUDirect. IEEE Transactions on Parallel and Distributed Systems, 2020, 31(1): 94- 110. doi: 10.1109/TPDS.2019.2928289
2	王琪, 张梅娟, 邓佳伟, 等. 基于PCIE转SATA多通道高速存储电路设计与原型验证. 电子技术应用, 2023, 49(3): 72- 76. URL
	WANG Q, ZHANG M J, DENG J W, et al. Design and prototype verification of multi-channel high-speed storage circuit base on PCIE to SATA. Application of Electronic Technique, 2023, 49(3): 72- 76. URL
3	杨佳丽. 基于PCIe总线的FPGA与PC间数据传输系统设计. 微型电脑应用, 2022, 38(4): 34- 36. doi: 10.3969/j.issn.1007-757X.2022.04.011
	YANG J L. Design of data transmission system between FPGA and PC based on PCIe bus. Microcomputer Applications, 2022, 38(4): 34- 36. doi: 10.3969/j.issn.1007-757X.2022.04.011
4	孙兆鹏, 周宽久. 基于PCIe的高性能FPGA-GPU-CPU异构编程架构. 计算机工程与科学, 2021, 43(4): 641- 651. doi: 10.3969/j.issn.1007-130X.2021.04.010
	SUN Z P, ZHOU K J. A high performance FPGA-GPU-CPU heterogeneous programming architecture based on PCIe. Computer Engineering & Science, 2021, 43(4): 641- 651. doi: 10.3969/j.issn.1007-130X.2021.04.010
5	赵陆, 文建平, 莫为, 等. 图像处理算法IP核的异构验证框架. 液晶与显示, 2021, 36(7): 1042- 1050. URL
	ZHAO L, WEN J P, MO W, et al. Heterogeneous verification framework of IP core for image processing algorithm. Chinese Journal of Liquid Crystals and Displays, 2021, 36(7): 1042- 1050. URL
6	刘斌. 芯片验证漫游指南: 从系统理论到UVM的验证全视界[M]. 北京: 电子工业出版社, 2018.
	LIU B. Walking guide to SoC verification: the panorama of verification from system to UVM[M]. Beijing: Publishing House of Electronics Industry, 2018. (in Chinese)
7	李龙乾, 方华, 冯姣, 等. 基于FPGA的PCIe接口逻辑设计与实现. 太赫兹科学与电子信息学报, 2022, 20(4): 385- 392. URL
	LI L Q, FANG H, FENG J, et al. Design and implementation of PCIe interface logic based on FPGA. Journal of Terahertz Science and Electronic Information Technology, 2022, 20(4): 385- 392. URL
8	REDDY K S, SOUJANYA P, SUDHA D K. Asic design and verification of AMBA APD protocol using UVM. International Journal of Innovative Technology and Exploring Engineering, 2020, 9(9): 636- 642. doi: 10.35940/ijitee.I7257.079920
9	FLAKEP, MOORBY P, GOLSON S, et al. Verilog HDL and its ancestors and descendants[C]//Proceedings of the ACM on Programming Languages. New York, USA: ACM Press, 2020: 1-90.
10	KULKARNI A, SAKTHIVEL S M. UVM methodology based functional verification of SPI protocol. Journal of Physics: Conference Series, 2020, 1716(1): 012035. doi: 10.1088/1742-6596/1716/1/012035
11	MARKUSSEN J, KRISTIANSEN L B, BORGLI R J, et al. Flexible device compositions and dynamic resource sharing in PCIe interconnected clusters using device lending. Cluster Computing, 2020, 23(2): 1211- 1234. doi: 10.1007/s10586-019-02988-0
12	徐航. 基于UVM及VIP技术的PCI Express接口验证[D]. 西安: 西安电子科技大学, 2018.
	XU H. The verification of PCI Express interface based on UVM and VIP technology[D]. Xi'an: Xidian University, 2018. (in Chinese)
13	周奇, 宣学雷, 贺光辉. 应用于FPGA的PCIe接口设计与验证. 微电子学与计算机, 2019, 36(7): 17- 21. URL
	ZHOU Q, XUAN X L, HE G H. Design and verification of PCIe interface for FPGA. Microelectronics & Computer, 2019, 36(7): 17- 21. URL
14	KARIM N I A, WAHAB A A A, NAZLI ALHADY S S, et al. PCIE IP validation process across process corner, voltage and temperature conditions. Journal of Physics: Conference Series, 2021, 1969(1): 012026. doi: 10.1088/1742-6596/1969/1/012026
15	TIAN S Q, GIECHASKIEL I, XIONG W J, et al. Cloud FPGA cartography using PCIe contention[C]//Proceedings of the 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). Washington D. C., USA: IEEE Press, 2021: 224-232.
16	RAGAMATHANA R, PRATHIBA A, BASHA S C. Design and verification of an ARM watchdog timer using UVM. International Journal of High Performance Systems Architecture, 2022, 11(2): 85. doi: 10.1504/IJHPSA.2022.127770
17	王清源, 高振斌, 杨晓龙. 基于UVM的PCIe桥接芯片验证平台设计. 微电子学与计算机, 2023, 40(5): 104- 111. URL
	WANG Q Y, GAO Z B, YANG X L. Verification design of PCIe bridge chip based on UVM. Microelectronics & Computer, 2023, 40(5): 104- 111. URL
18	任传宝, 崔建国, 鲁迎春, 等. 应用直接编程接口技术提高片上系统的UVM验证重用性. 微电子学与计算机, 2021, 38(6): 20-26, 32. URL
	REN C B, CUI J G, LU Y C, et al. Using direct programming interface technology to improve the reusability of UVM verification of system on chip. Microelectronics & Computer, 2021, 38(6): 20-26, 32. URL
19	CHANDRA K, JAGTAP A P, RANJAN N, et al. Design of PCIe-DMA bridge interface for high speed ethernet applications[C]//Proceedings of the 2nd International Conference on Advanced Computational and Communication Paradigms (ICACCP). Washington D. C., USA: IEEE Press, 2019: 1-5.
20	MOON S J, YE X N, WANG K A, et al. Application of IEEE-370 for PCIe interconnect test with 2X-thru de-embedding[C]//Proceedings of the IEEE International Joint EMC/SI/PI and EMC Europe Symposium. Washington D. C., USA: IEEE Press, 2021: 835-839.
21	HUANG X, HE X, HE Z R, et al. Using UVM testbench to generate the analog stimuli. DEStech Transactions on Computer Science and Engineering, 2019, 1- 10.
22	VASA M, LIAO C L, KUMAR S, et al. PCIe Gen-5 design challenges of high-speed servers[C]//Proceedings of the 29th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS). Washington D. C., USA: IEEE Press, 2020: 1-3.
23	DAS SHARMA D. PCI express 6.0 specification: a low-latency, high-bandwidth, high-reliability, and cost-effective interconnect with 64.0 GT/s PAM-4 signaling. IEEE Micro, 2021, 41(1): 23- 29.
24	TAN M T, WAN J P, ZHOU Z, et al. Invisible probe: timing attacks with PCIe congestion side-channel[C]//Proceedings of the IEEE Symposium on Security and Privacy (SP). Washington D. C., USA: IEEE Press, 2021: 322-338.
25	孙欣欣, 李娟, 田粉仙, 等. 一种基于PCIE总线的DMA引擎研究. 云南大学学报(自然科学版), 2021, 43(3): 444- 450. URL
	SUN X X, LI J, TIAN F X, et al. Research on a DMA engine based on PCIE bus. Journal of Yunnan University (Natural Sciences Edition), 2021, 43(3): 444- 450. URL
26	MARKUSSEN J, KRISTIANSEN L B, HALVORSEN P, et al. SmartIO: zero-overhead device sharing through PCIe networking[J]. ACM Transactions on Computer Systems, 2020, 38(2): 1-2.
27	LIM S, CHA K. Shared memory model over a switchless PCIe NTB interconnect network. Journal of Information Storage and Processing Systems, 2022, 18, 159- 172.

[1]	张清国, 张勇, 张伟, 席瑞洁. 基于蜂窝结构的改进混合无线传感器网络覆盖优化算法[J]. 计算机工程, 2022, 48(12): 172-179.
[2]	汪荣峰, 胡敏. 基于扫描线的卫星区域覆盖分析算法[J]. 计算机工程, 2020, 46(1): 243-246,254.
[3]	郁诺. 有约束的三维RFID读写器网络规划方法[J]. 计算机工程, 2017, 43(6): 59-65.
[4]	高春玲,李孜,孙泽宇,邢萧飞. 无线传感器网络中多目标K覆盖保持算法[J]. 计算机工程, 2016, 42(7): 59-64,71.
[5]	杨修涛,谷小秋. 基于指令的数字信号处理器验证[J]. 计算机工程, 2015, 41(9): 97-102.
[6]	杨本臣,王翠琴,王馨蕊. 基于改进接收信号强度指示的四面体模型井下定位研究[J]. 计算机工程, 2015, 41(8): 286-290,295.
[7]	张良,王天成,王健,李华伟,郭建. PCIE 协议栈模拟验证平台的设计和实现[J]. 计算机工程, 2015, 41(6): 287-293.
[8]	邱奉美,李怀忠. 无线传感器网络DV-Hop定位算法的改进[J]. 计算机工程, 2014, 40(8): 15-20,26.
[9]	马佳敏，潘理，姚颉文. 面向新一代固件接口标准的固件模糊测试系统[J]. 计算机工程, 2014, 40(7): 277-280.
[10]	刘畅，郭阳. 基于覆盖率驱动的高性能DSP指令集验证方法[J]. 计算机工程, 2014, 40(6): 317-320.
[11]	王颖, 石昊旸. 改进的无线传感器网络DV-Hop定位算法[J]. 计算机工程, 2012, 38(7): 66-69.
[12]	王轶, 蒋同海, 董军, 周喜. 基于路径覆盖插桩的可执行代码测试工具实现[J]. 计算机工程, 2012, 38(5): 35-37,40.
[13]	鲁旭阳, 张效义, 刘广怡. 稀疏无线传感器网络的节点自定位算法[J]. 计算机工程, 2012, 38(18): 83-86.
[14]	袁佳琳, 高建华. 基于改进FSM的RBAC测试集约简方法[J]. 计算机工程, 2012, 38(17): 42-45,48.
[15]	向辉, 彭力, 闻继伟. 高效节能的视觉传感器网络目标覆盖算法[J]. 计算机工程, 2012, 38(16): 113-116.

选择文件类型/文献管理软件名称

选择包含的内容