摘要： 传统Radix-4 Booth编码在负值部分积生成过程中会产生大量求补操作，影响乘法器的工作效率。为此，提出一种重组部分积的乘法器优化设计。通过增加一个“或”门运算以及重组硬连线，避免求补过程中的加法运算，并且未产生多余的部分积。在32位乘法器上的验证结果表明，该设计能有效减小关键路径延迟和芯片面积消耗。

关键词: Radix-4 Booth编码, 乘法器, 部分积, 关键路径延迟, 芯片面积消耗

Abstract: The traditional Radix-4 Booth encoding will produce the complement computing operation emerged in the process of negative partial product generation, which influences the word efficiency for multiplier. Aiming at this problem, this paper puts forward a multiplier optimal design of recombining partial products. By adding an “or” gate operation and simple hard-wired recombinant, it avoids addition operation in the complement computing process, and does not generate redundant partial product. The validated result on 32-bit multiplier shows that the design can effectively reduce the critical path delay and chip area consumption.

Key words: Radix-4 Booth encoding, multiplier, partial product, key path delay, chip area consumption

中图分类号: 

• TN492