摘要： 在使用硬件电路进行H.264编码时，为提高帧内预测运算速度，减少硬件电路面积，提出一种基于现场可编程门阵列(FPGA)的H.264帧内预测硬件电路的实现和优化解决方案。利用FPGA的并行处理能力和同模式下帧内预测数据冗余对硬件电路进行优化。使用Verilog语言进行模块设计，仿真平台为Modelsim，在Altera CycloneII EP2C20F484C上的实现，验证了该硬件电路结构的高效性及实用性。

关键词: 帧内预测, H.264视频编码标准, 现场可编程门阵列, 硬件结构, Verilog HDL语言, 并行处理

Abstract: In order to improve intra prediction operation speed and reduce the Field Programmable Gate Array(FPGA) hardware resources consumption. An optimized hardware architecture is proposed for an intra prediction of H.264 based on FPGA. The redundancy of prediction values in the same prediction mode and the parallel processing ability are also fully utilized to optimize hardware architecture. The proposed architecture is implemented in Verilog HDL and verifies that it is effective and practical in Altera Cyclone II EP2C20F484C8 FPGA.

Key words: intra prediction, H.264 video coding standard, Field Programmable Gate Array(FPGA), hardware structure, Verilog HDL language, parallel processing

中图分类号: 

• TP391.41