摘要：

针对加解密运算中微处理器性能低、功耗高,以及专用电路灵活度受限的问题,提出基于运算部件粗粒度可重构的密码加速单元及其架构。给出密码运算的原子运算并实例化为运算部件,以原子运算部件为重构粒子,路由表负责配置运算部件互连网络以组合运算,参数表负责配置密码算法参数。通过生成路由表与参数表配置信息,对密码加速单元进行粗粒度重构。该架构在TSMC 0.13 μm时可工作在350 MHz的时钟频率下。实验结果表明,提出的架构兼具微处理器与专用电路的优点,支持多种密码算法,所需的信息量和资源消耗少,并具有较好的性能面积比。

关键词: 密码算法, 粗粒度, 可重构, 运算部件阵列, 路由器阵列, 路由表

Abstract:

Facing with the poor performance and high power consumption of microprocessor and inflexibility of ASIC in encryption and decryption computation,coarse-grain reconfigurable cryptographic algorithm processing architecture based on operating elements is proposed.This paper extracts atomic operations and instantiates them as processing elements.Operating elements are taken as reconfigurable gains,coupled with routing table and parameter table.Routing table is in charge of configuring interconnection network of operating elements while parameter table is responsible for configuring cryptographic algorithm parameters.By generating routing table and parameter table information according to different cryptographic algorithms,cryptographic accelerator is coarse-grain reconfigured to support various cryptographic algorithms.The circuit reaches clock frequency of 350 MHz using TSMC 0.13 μm cell library.Experimental results show that the architecture has both the advantages of microprocessor and ASIC and it flexibly supports various cryptographic algorithms.The required amount of information and resource consumption is less,and has better performance area ratio.

Key words: cryptographic algorithm, coarse-grain, reconfigurable, operating element array, router array, routing table

中图分类号: 

• TP301.6