| 参考文献
［1］MARCULESCU R,OGRAS U Y,PEH L S,et al.Outstanding Research Problems in NoC Design:System,Microarchitecture,and Circuit Perspectives［J］.IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems,2009,28(1):3-21.
［2］MA Sheng,HUANG Libo,LAI Mingche,et al.Networks-on-chip:From Implementations to Programm-ing Paradigms［M］.San Francisco,USA:Morgan Kaufmann Publishers Inc.,2014.
［3］BENINI L,MICHELI G.Networks on Chips:A New SoC Paradigm［J］.Computer,2002,35(1):70-78.
［4］DAS R,EACHEMPATI S,MISHRA A K,et al.Design and Evaluation of a Hierarchical On-chip Interconnect for Next-generation CMPs［C］//Proceedings of IEEE 15th International Symposium on High Performance Computer Architecture.Washington D.C.,USA:IEEE Press,2009:175-186.
［5］ZARKESH P,BEZERRA G B P,Forrest S,et al.Hybrid Network on Chip(HNoC):Local Buses with a Global Mesh Architecture［C］//Proceedings of the 12th ACM/IEEE International Workshop on System Level Interconnect Prediction.New York,USA:ACM Press,2010:9-14.
［6］LOUCIF S.Performance Evaluation of Hierarchical-torus NoC［C］//Proceedings of the 27th International Con-ference on Advanced Information Networking and Applications Workshops.Washington D.C.,USA:IEEE Press,2013:837-842.
［7］孔峰,韩国栋,沈剑良,等.一种基于Mesh结构的新型层次化片上网络拓扑结构［J］.电子与信息学报,2014,36(10):2536-2540.
［8］SWAMINATHAN K,GOPI S,LAKSHMINARAYANAN G,et al.A Novel Hybrid Topology for Network on Chip［C］//Proceedings of the 27th Canadian Conference on Electrical and Computer Engineering.Washington D.C.,USA:IEEE Press,2014:1-6.
［9］ZHOU Y,JIAN G,HAN G.Parametric Hierarchical Mesh Interconnected Structure for Network-on-Chip［C］//Proceedings of the 6th IEEE International Conference on Software Engineering and Service Science.Washington D.C.,USA:IEEE Press,2015:193-197.
［10］INAM O,KHANJARI S,VANDERBAUWHEDE W.Shortest Path Routing Algorithm for Hierarchical Interconnection Network-on-Chip［J］.Procedia Computer Science,2015,56(1):409-414.
［11］SCHLEY G,RADETZKI M.Fault Tolerant Routing for Hierarchically Organized Networks-on-Chip［C］//Pro-ceedings of the 23rd Euromicro International Conference on Parallel,Distributed and Network-Based Processing.Washington D.C.,USA:IEEE Press,2015:379-386.
［12］张家齐,沈剑良,朱珂.FPGA并行时序驱动布局算法［J］.计算机工程,2017,43(2):98-104.
［13］DALLY W,TOWLES B.Principles and Practices of Interconnection Networks［M］.San Francisco,USA:Morgan Kaufmann Publishers Inc.,2004.
［14］BEN-ITZHAK Y,ZAHAVI E,CIDON I,et al.HNOCS:Modular Open-source Simulator for Heterogeneous NoCs［C］//Proceedings of 2012 International Conference on Embedded Computer Systems.Washington D.C.,USA:IEEE Press,2012:51-57.
［15］WINTER M,PRUSSEIT S,GERHARD P F.Hierarchical Routing Architectures in Clustered 2D-mesh Networks-on-chip［C］//Proceedings of SoC Design Conference.Washington D.C.,USA:IEEE Press,2010:388-391.
［16］韩国栋,孔峰,沈剑良.基于源区域路径选择的层次化片上网络路由算法［J］.计算机应用,2014,34(10):2761-2765.
［17］MANEVICH R,CIDON I,KOLODNY A.Design and Dynamic Management of Hierarchical NoCs［J］.Micro-processors and Microsystems,2016,40(C):154-166.
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