摘要： 介绍了一种2-D × 8 8 IDCT处理器系统的ASIC架构,采用分布算法、并行结构、流水线设计。对于常用的ROM查找表实现方案,该文提出了一种以寄存器、加法器构建的替代电路的新方案,同样省去了乘法器,避免了使用ROM,且硬件代价与使用ROM相比还略有减小,最终提高了数据的吞吐量,达到2.4GB/s,满足了MP@HL标准的HDTV的108MHz的频率要求,而同样工艺条件下采用ROM查找表则只能达到90MHz的频率。

关键词: 逆离散余弦变换, 流水线, IDCT/DCT, 查找表(LUT), 分布算法

Abstract: An design of 8×8 2-D IDCT processor is described, which adopts distributed arithmetic(DA), concurrent architecture and pipelining. Instead of implementation of using ROM look-up table, this paper proposes a new approach which constructs the circuit using registers and adders. The multipliers are also avoided, and the hardware cost should not be increased. However, it improves the data throughput and achieves the requirements of 108MHz which meets the MP@HL standard on the MPEG2, but previous design only achieves 90MHz frequency using ROM look- up table at the same conditions.

中图分类号: 

• TN402