摘要： 全新的基于全定制传输门结构42压缩高性能乘法生成器能根据用户输入自动产生并行乘法器的Verilog代码,并对Wallace Tree 的连线进行了优化。最后在末级加法器阶段,生成器能根据到达的时延不同自动选择不同加法器最优的分段。在设计某些乘法器时生成器产生的代码综合结果在面积增加10%~20%左右时比Synopsys Design Ware库里相应的乘法器快5%~9%左右。

关键词: 并行乘法器, 全定制, 改进的Booth编码, WallaceTree, 部分积压缩

Abstract: A new high performance multiplier generator based on full-custom pass-transistor logic 42 compressors can produce Verilog codes of parallel multipliers according to parameters input by users and optimizes the irregular connection of Wallace tree. Finally the generator can automatically select the best partition point for different types of adders according to various of input delays in the final adder stage. Synthesis results show that the generated multipliers are about 5% to 9% faster than the counterparts of Synopsys Design Ware with only 10%-20% area overhead.

中图分类号: 

• TP332