摘要： 提出一种新的基于连续和交替序列编码的测试数据压缩方案。采用变长到变长的编码方式对测试序列中连续的“0”和“1”以及交替变化位的长度进行编码。代码字由前缀和尾部组成，用前缀表明编码的序列类型。该方案的解压电路结构简单，所需的硬件开销较小。在ISCAS’89基准电路上的实验结果表明，该编码方法能有效压缩测试数据。

关键词: 测试数据压缩, Golomb码, FDR码, 系统芯片

Abstract: A new test data compression technique based on encoding series and alternation sequences is proposed. It is a variable-to- variable-length code based on encoding lengths of runs of 0 s and 1 s, as well as alternating bits in test sequences. The code word consists of prefix and tail, the scheme uses prefix to indicate the type of sequence. Due to its simple architecture, the additional hardware overhead that the decompression circuit requires is very small. Experimental results for the ISCAS’89 benchmark circuits show that this technique can efficiently compress test data.

Key words: test data compression, Golomb codes, FDR codes, System on Chip(SoC)

中图分类号: 

• TP391