摘要: 根据不同环境对安全散列算法安全强度的不同要求,采用可重构体系结构的思想和方法,设计一种可重构的散列函数密码芯片。实验结果表明,在Altera Stratix II系列现场可编程门阵列上,SHA-1, SHA-224/256, SHA-384/512的吞吐率分别可达到727.853 Mb/s, 909.816 Mb/s和1.456 Gb/s。
关键词:
可重构密码芯片,
安全散列算法,
现场可编程门阵列
Abstract: According to different needs to security hash algorithms under different circumstances, this paper adopts the thought and method of the reconfigurable architecture, and designs a reconfigurable hash cryptographic chip. Experimental results based on FPGA of the family of Stratix II of Altera Corporation show that the proposed system reaches throughput values equal to 727.853 Mb/s for SHA-1, 909.816 Mb/s for SHA-224/256, and 1.456 Gb/s for SHA-384/512 respectively.
Key words:
reconfigurable cryptographic chip,
security hash algorithms,
Field Programmable Gate Array(FPGA)
中图分类号:
李 淼;徐金甫;戴紫彬;杨晓辉. 可重构散列函数密码芯片的设计与实现[J]. 计算机工程, 2010, 36(06): 131-132.
LI Miao; XU Jin-fu; DAI Zi-bin; YANG Xiao-hui. Design and Implementation of Reconfigurable Hash Function Cryptographic Chip[J]. Computer Engineering, 2010, 36(06): 131-132.