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计算机工程 ›› 2011, Vol. 37 ›› Issue (20): 242-245. doi: 10.3969/j.issn.1000-3428.2011.20.083

• 工程应用技术与实现 • 上一篇    下一篇

基于FPGA的飞控计算机多路串行通信设计

喻少林,韩 波,李 平   

  1. (浙江大学导航制导与控制研究所,杭州 310027)
  • 收稿日期:2011-03-21 出版日期:2011-10-20 发布日期:2011-10-20
  • 作者简介:喻少林(1982-),男,硕士研究生,主研方向:嵌入式系统,无人驾驶飞机导航、制导与控制;韩 波,副研究员、博士;李 平,教授、博士、博士生导师
  • 基金资助:
    国家“863”计划基金资助项目(2006AA10Z204)

Design of Multi-serial Communication for Flight Controlling Computer Based on FPGA

YU Shao-lin, HAN Bo, LI Ping   

  1. (Institute of Navigation Guidance and Control, Zhejiang University, Hangzhou 310027, China)
  • Received:2011-03-21 Online:2011-10-20 Published:2011-10-20

摘要: 飞控计算机与外设进行多路串行通信时必须进行串口扩展,但传统的通用异步接发器(UART)扩展接口芯片引脚多、体积大,与其他器件的接口复杂。为此,采用一块现场可编程门阵列芯片,利用verilog HDL编程,设计通用异步收发器单元、数据接收控制器、数据发送控制器、双口随机存取存储器等模块,实现飞控计算机的10路串行通信,减少电路面积和功耗。在ISE9.1i上的仿真结果表明,该设计可实现数据的正确传输。

关键词: 现场可编程门阵列, 通用异步收发器, 数据接收控制器, 数据发送控制器, 双口随机存取存储器

Abstract: The serial ports must be expanded when the flight controlling computer communicates with exterior devices by multi-serial communi- cation, with the characteristic of too many pins and big figure, usual Universal Asynchronous Receiver/Transmitter(UART) chip makes the circuit large and high-consumed. Aiming at these problems, this paper chooses a Field Programmable Gate Array(FPGA) chip, programming with verilog HDL, designs and integrates ten UART cells, data-receive controller, data-send controller and dual-port Random Access Memory(RAM), achieves ten channels of serial communication of the flight controlling computer, and manages to make the circuit much simpler. It is confirmed that the design scheme is correct by simulating and test the design result with ISE9.1i.

Key words: Field Programmable Gate Array(FPGA), Universal Asynchronous Receiver/Transmitter(UART), data-receive controller, data-send controller, dual-port Random Access Memory(RAM)

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