计算机工程

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基于FPGA模拟的阻变神经网络加速器评估方法研究与设计

  

  • 发布日期:2020-12-18

A FPGA-based Emulation for Resistive Neural Network Accelerator

  • Published:2020-12-18

摘要: 由于阻变器件的非理想特性,基于阻变器件的存算一体神经网络加速器需要在架构设计初期进行精确细致的仿真评 估,以确保神经网络的精度符合设计要求。但传统阻变神经网络加速器软件模拟器仿真速度慢,难以应对大规模网络的架构 评估需求。为加快仿真速度,本文提出一种基于 FPGA 模拟的阻变神经网络加速器评估方法,通过分析现有阻变神经网络加 速器的架构通用性,利用 FPGA 资源的高度并行性和运行时指令驱动的灵活模拟方式,通过对有限硬件资源的分时复用,该 FPGA 模拟器可支持主流阻变神经网络加速器架构和指令集的功能模拟,并针对主流网络给出详尽的性能评估。结果表明, 对不同规模的忆阻器阵列,本文提出的阻变神经网络加速器评估方法相较软件仿

Abstract: 】According to the non-ideal variation of Resistive devices like Resistive random access memory (ReRAM), the processing-in-memory (PIM) architectural exploration needs a careful evaluation during the accelerator design. However, given the cycle-true simulation of ReRAM in the massive resources, the simulation time increases sharply especially for large-scale DNNs. After analyzing current PIM accelerators, we propose a field programmable gate array (FPGA)-based emulation for resistive neural network accelerator to cater for general PIM deep neural network (DNN) accelerator architecture and instruction set architecture (ISA) to accelerate the simulation. The emulator evaluates popular neural networks detailly via massive parallelism and flexible instructions. The result shows that the accelerator gets performance