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计算机工程 ›› 2012, Vol. 38 ›› Issue (23): 255-258. doi: 10.3969/j.issn.1000-3428.2012.23.063

• 工程应用技术与实现 • 上一篇    下一篇

高性能并行Turbo译码器的VLSI设计

陈绪斌,曹嘉麟,陈 赟,曾晓洋   

  1. (复旦大学专用集成电路与系统国家重点实验室,上海 201203)
  • 收稿日期:2012-03-12 出版日期:2012-12-05 发布日期:2012-12-03
  • 作者简介:陈绪斌(1986-),男,硕士研究生,主研方向:纠错码,VLSI设计;曹嘉麟,硕士研究生;陈 赟,讲师;曾晓洋,教授、博士生导师
  • 基金资助:
    国家“863”计划基金资助项目(SQ2008AA01ZX1480432);国家科技重大专项基金资助项目“新一代宽带无线移动通讯网”(2011ZX 03003-003-03)

VLSI Design of High Performance Parallel Turbo Decoder

CHEN Xu-bin, CAO Jia-lin, CHEN Yun, ZENG Xiao-yang   

  1. (State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China)
  • Received:2012-03-12 Online:2012-12-05 Published:2012-12-03

摘要: 提出一种高度并行的Turbo译码器。该译码器包含32个并行的基-4子译码器,采用改进的滑窗译码流程和存储单元划分方案,使吞吐率最高提升43.2%。在SMIC 0.13 μm工艺下,该译码器包含194万等效门,在294 MHz时钟频率和5.5次迭代下,吞吐率可达 1.19 Gb/s,满足4G移动通信标准LTE-Advanced的峰值吞吐率要求。

关键词: Turbo码, 译码器, 并行结构, 基-4, 4G移动通信

Abstract: This paper presents a highly-parallel Turbo decoder architecture. It utilizes 32-parallel radix-4 component decoders and its throughput is increased by 43.2% at most with modified sliding window and memory partition scheme. The proposed decoder is implemented in SMIC 0.13 μm technology, which has 1.94 M equivalent gate counts and achieves 1.19 Gb/s running at 294 MHz with 5.5 iterations. It meets the peak data rate requirement of 4G mobile communication standard LTE-Advanced.

Key words: Turbo code, decode, parallel architecture, radix-4, 4G mobile communication

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