计算机工程 ›› 2013, Vol. 39 ›› Issue (7): 177-180.doi: 10.3969/j.issn.1000-3428.2013.07.040

• 安全技术 • 上一篇    下一篇

分组密码算法SM4的低复杂度实现

王晨光,乔树山,黑 勇   

  1. (中国科学院微电子研究所,北京 100029)
  • 收稿日期:2012-08-23 出版日期:2013-07-15 发布日期:2013-07-12
  • 作者简介:王晨光(1988-),男,硕士研究生,主研方向:专用集成电路设计;乔树山,副研究员、博士;黑 勇,研究员、博士
  • 基金项目:
    “核高基”重大专项“基于可编程逻辑阵列IP的SoC设计”(2009ZX01034-002-004-007(002))

Low Complexity Implementation of Block Cipher SM4 Algorithm

WANG Chen-guang, QIAO Shu-shan, HEI Yong   

  1. (Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China)
  • Received:2012-08-23 Online:2013-07-15 Published:2013-07-12

摘要: 针对分组密码算法SM4中加解密算法与密钥扩展算法的相似性,提出一种将加解密模块与密钥扩展模块复用的基本架构,通过对具体实现结构的分析与选择,使控制逻辑复杂度、复用模块复杂度以及系统吞吐量之间得到权衡。基于该架构设计SM4加解密IP核,在现场可编程门阵列上占用的资源仅为传统设计的55%,基于SMIC 0.18 μm数字CMOS工艺的综合结果显示,仅用0.079 mm2即可实现100 Mb/s的数据吞吐量。实验结果表明,该结构可以有效地降低SM4算法的实现复杂度。

关键词: SM4算法, 分组密码算法, 低复杂度, 硬件复用, 现场可编程门阵列, 特定用途集成电路实现

Abstract: A basic architecture is proposed for reducing the implementation complexity of SM4 block cipher. The architecture reuses the hardware of encryption/decryption and key expansion module because the encryption/decryption algorithm is very similar with the key expansion algorithm. Optimum trade-off among control-logic complexity, reused-module complexity and throughput is realized through careful analysis and choose of specific realization. A SM4 cipher IP is designed based on this architecture. The designed IP’s cost is only 55% of the traditional design in Field Programmable Gate Array(FPGA). The IP is also synthesized under the SMIC 0.18 μm CMOS process. Its area is 0.079 mm2 with 100 Mb/s throughput. Experimental results of synthesis show that the proposed architecture can reduce the implementation complexity of SM4 block cipher efficiently.

Key words: SM4 algorithm, block cipher algorithm, low complexity, hardware reuse, Field Programmable Gate Array(FPGA), Application Specific Integrated Circuit(ASIC) implementation

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