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计算机工程 ›› 2010, Vol. 36 ›› Issue (16): 216-218. doi: 10.3969/j.issn.1000-3428.2010.16.078

• 工程应用技术与实现 • 上一篇    下一篇

高速SDRAM控制器的嵌入式设计

邓耀华1,2,刘桂雄1,吴黎明2   

  1. (1. 华南理工大学机械与汽车工程学院,广州 510643;2. 广东工业大学信息工程学院,广州 510006)
  • 出版日期:2010-08-20 发布日期:2010-08-17
  • 作者简介:邓耀华(1978-),男,博士研究生,主研方向:嵌入式系统;刘桂雄,教授、博士、博士生导师;吴黎明,教授、硕士
  • 基金资助:

    粤港关键领域重点突破基金资助项目(20080102-5)

Embedded Design of High-speed SDRAM Controller

DENG Yao-hua1,2, LIU Gui-xiong1, WU Li-ming2   

  1. (1. School of Mechanical and Automotive Engineering, South China University of Technology, Guangzhou 510643;2. School of Information Engineering, Guangdong University of Technology, Guangzhou 510006)
  • Online:2010-08-20 Published:2010-08-17

摘要:

为适应高数据吞吐速率的应用场合,在分析同步动态随机存储器(SDRAM)控制器工作原理的基础上,研究支持高数据处理效率可连续读写操作的存储控制算法。利用现场可编程门阵列设计SDRAM嵌入式存储控制器,采用CMD命令形式,根据猝发长度分配连续读写延时,通过数据通道控制与读写操作协同工作提高数据处理效率。测试结果表明,该控制器运行频率高于100 MHz,数据处理效率大于95%,适用于视频采集数据缓存及大型LED显示控制中。

关键词: 同步动态随机存储器, 现场可编程门阵列, 连续读写指令

Abstract:

To meet the demands of application situation of mass data throughput, this paper researches memorizing control algorithm which supports high treatment efficiency and data continuous read/write operation, and uses Field Programmable Gate Array(FPGA) to design SDRAM embedded control algorithm. The controller uses CMD order mode, assigns time-delay of continuous read/write based on burst length, enhances the data processing efficiency by team working between data channel control and read/write operation. Testing results show that running frequency of this controller is higher than 100 MHz, data processing efficiency is above 95%, and it applies to data buffer of video acquisition and large size display control of LED.

Key words: Synchronous Dynamic Random Access Memory(SDRAM), Field Programmable Gate Array(FPGA), continuous read/write instruction

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