摘要： 基于加解密算法中访存频繁、循环执行与其边界和数据运算长度存在一一对应关系的特性，提出一个快速实现多种算法的指令集，其中包括基于该指令集五级流水硬件的实现。从软件和硬件层面上设计并实现一个完整的通用安全协处理器原型系统。实验表明该协处理器具有良好的结构和功能。

关键词: 密码学, 安全协处理器, IC设计, 指令集

Abstract: Based on the features of frequently accessing memory, recurrent execution and the minimum/maximum loop boundary decided by input length in a cryptography algorithm, this paper proposes an instruction set architecture, including corresponding hardware realization of five pipeline stages. It designs and implements an entire co-processor including hardware and software implementation. Experimental results indicate that there are characters of excellent structure and function in the co-processor.

Key words: cryptography, security co-processor, IC design, instruction set

中图分类号: 

• TP332