摘要： 提出一种时序优化的通用FPGA装箱算法。将配置电路与用户电路转化为有向图，解决子图同构问题。将线网延时作为变量，定义关键度，以此为代价函数进行装箱，达到优化时序的目的。在VPR平台上进行实验，结果表明，该算法的时序性能较优，并可应用于不同的可配置逻辑块结构中。

关键词: 现场可编程门阵列, 工艺映射, 装箱算法, 时序优化

Abstract: A universal timing optimization oriented FPGA packing algorithm is proposed in this paper. Configure and user circuits are converted to directed graphs to solve the sub-graph isomorphism problem. Aiming for timing optimization, net delay is used as variable to define the criticality, which is used for cost function to guide packing procedure. Experimental results on VPR platform prove this algorithm performs less timing delay than other similar packing algorithms, and can applied in various kinds of FPGA CLBs.

Key words: Field Programmable Gate Array(FPGA), technology mapping, packing algorithm, timing optimization

中图分类号: 

• TP303