[1]何允灵,秦娟,王佳,等.SoC处理器的电源管理系统设计[J].计算机工程,2008,34(16):262-264.
[2]刘丽娟,杨兵初,倪兰,等.PDN电源地平面去耦电容网络设计[J].中南大学学报(自然科学版),2013(10):4088-4093.
[3]WU H,ZHAO Y,WHITE M H.Modeling of MOSFET gate leakage for high k gate dielectrics[C]//Proceedings of 2005 International Semiconductor Device Research Symposium.Washington D.C.,USA:IEEE Press,2005:380-381.
[4]ROY K,MUKHOPADHYAY S,MAHMOODIMEIMAND H.Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits[J].Proceedings of the IEEE,2003,91(2):305-327.
[5]SU H,SAPATNEKAR S S,NASSIF S R.An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts[C]//Proceedings of International Symposium on Physical Design.Washington D.C.,USA:IEEE Press,2002:68-73.
[6]FU J,LUO Z,HONG X,et al.A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery[C]//Proceedings of 2004 Asia and South Pacific Design Automation Conference.Washington D.C.,USA:IEEE Press,2004:505-510.
[7]WANG K,MAREK-SADOWSKA M.On-chip power supply network optimization using multigrid-based technique[C]//Proceedings of 2003 Design Automation Conference.Washington D.C.,USA:IEEE Press,2003:113-118.
[8]LI H,FAN J,QI Z,et al.Partitioning-based approach to fast on-chip decoupling capacitor budgeting and minimization[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2006,25(11):2402-2412.
[9]KANG N L,CAI N Y,ZOU N Y,et al.Fast decoupling capacitor budgeting for power/ground network using random walk approach[C]//Proceedings of Asia and South Pacific Design Automation Conference.Washington D.C.,USA:IEEE Press,2007:751-756.
[10]ZHAO S,ROY K,KOH C K.Decoupling capacitance allocation for power supply noise suppression[C]//Proceedings of 2001 International Symposium on Physical Design.New York,USA:ACM Press,2001:66-71.
[11]ZHAO M,PANDA R,SUNDARESWARAN S,et al.A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming[C]//Proceedings of the 43rd ACM/IEEE Design Automation Conference.Washington D.C.,USA:IEEE Press,2006:217-222.
[12]HO C W,RUEHLI A E,BRENNAN P A.The modified nodal approach to network analysis[J].IEEE Transactions on Circuitsand Systems,1975,22(6):504-509.
[13]WANG X,CAI Y,TAN X D,et al.An efficient decoupling capacitance optimization using piecewise polynomial models[C]//Proceedings of 2009 Design,Automation and Test in Europe Conference and Exhibition.Washington D.C.,USA:IEEE Press,2009:1190-1195.
[14]KAHNG A B,LIU B,TAN X D.Efficient decoupling capacitor planning via convex programming methods[C]//Proceedings of International Symposium on Physical Design.New York,USA:ACM Press,2006:102-107.
[15]CHARANIA T,OPAL A,SACHDEV M.Analysis and design of on-chip decoupling capacitors[J].IEEE Transactions on Very Large Scale Integration Systems,2013,21(4):648-658.
[16]LEE D,KWONG W,BLAAUW D,et al.Analysis and minimization techniques for total leakage considering gate oxide leakage[C]//Proceedings of 2003 Design Automation Conference.Washington D.C.,USA:IEEE Press,2003:175-180.
[17]吴汉明,吴关平,吴金刚,等.纳米集成电路大生产中新工艺技术现状及发展趋势[J].中国科学:信息科学,2012,42(12):1509-1528. |