摘要： 提出一种改进的基于剩余数系的Montgomery模乘算法。该算法通过对相对固定的参数进行预计算，从而减少运算过程中模乘运算的次数，与Bajard J C提出的算法(IEEE计算机会刊，2004年第6期)相比减少300/(2k+8)。同时基于改进算法提出数据长度可伸缩的硬件模乘器结构设计，并在0.18 μm SMIC工艺下进行综合。性能分析表明，该设计在运算速度上有明显的提高。
关键词:
剩余数系,
模乘,
可伸缩设计,
硬件实现
Abstract: This paper presents an improved Residue Number System(RSN) Montgomery modular multiplication algorithm, which is optimized by pre-computing the constant parameter. Compared to the Bajard J C(IEEE Transactions on Computers, 2004, No.6) algorithm, the number of modular multiplication is reduced by 300/(2k+8) percent. A hardware design of scalable modular multiplier is proposed, which is implemented on 0.18 μm SMIC process. Result shows that the design has advanced performance.
Key words:
Residue Number System(RSN),
modular multiplication,
scalable design,
hardware implementation
中图分类号:
杨同杰, 戴紫彬, 杨晓辉. 一种可重构模乘器的硬件设计[J]. 计算机工程, 2011, 37(13): 238-240.
YANG Tong-Jie, DAI Zi-Ban, YANG Xiao-Hui. Hardware Design of Scalable Modular Multiplier[J]. Computer Engineering, 2011, 37(13): 238-240.