摘要： ERES-ET是复旦大学与华东计算技术研究所合作研制的计算机设计模拟验证环境。它已被用于数个新研制计算机的设计验证。典型的应用有,对上海交通大学研制的RISC-3JI微处理机的设计验证,以及对华北计算所研制的面向LISP语言的TJ-LISP计算机的设计验证．因验证过程大致相同,主要介绍RISC-3JI机的设计验证。

关键词: 硬件描述语言, 模拟, 设计验证

Abstract: ERES-ET is a computer design simulation and verification environment which was developed by Fudan university and East China Institute of Computer Technologies. It has been used in design verification of a number of newly designed computers.Among them there arc RISC-3J1 microprocessor designed by Shanghai Jiaotong university and TJ-LISP which is a LISP oriented computer designed by North China Institute of Computer Technologies.This paper takes emphasis on the design verification of RISC-3J1. Design errors both in hardware and software were discovered by ERES-ET, showing its efficiency.

中图分类号: 

• TP302