摘要： 从编译的角度对嵌入式DSP核提出了设计方法,并用此方法设计了16位定点DSP核。该DSP核具有16位的数据位宽和24位的指令位宽,所有的指令都是在5级流水线中完成的。最后实现在0.35μm CMOS标准单元库支持下,工作频率可以达到80MHz以上。

关键词: DSP设计, 设计方法, 体系结构, 编译技术

Abstract: This paper presents a design technology from a compilation view for embedded DSP processors. Under the guidance of this method, it designs a 16 bits DSP core. This core has a data-width of 16 bits and an instruction-width of 24 bits with all the instructions completed within a five- stage pipeline. This DSP core is realized in a 0.35μm CMOS technology and can work over 80MHz.

中图分类号: 

• TP332