摘要： 采用了一种改进的基—4 BOOTH编码方案,设计了一种高速32×32-b定/浮点并行乘法器。乘法器电路利用CPL逻辑来实现。通过对关键延时路径中的(4:2)压缩器和64位加法器的优化设计,可以在20ns内完成一次乘法运算。乘法器的设计由0.45um的双层金属CMOS工艺实现,工作电压为3.3V,用于自适应数字滤波运算中。

关键词: 乘法器, BOOTH编码, CPL

Abstract: This paper presents a high-speed 32×32-b multiplier with modified Booth encoders.In order to improve speed,it chooses CPL as the best logic style to implement the multiplier.The multiplier ciucuits are simulated and fabricated using 0.45μmdouble metal CMOS technology, and by optimizing both the propagation time of the(4:2)compressors and the propagation time of the 64-bit adder,a 20-ns multiplication time is achieved at a 3.3-V powersupply .The multiplier is used in a DSP system for self-adaptive filtering.

中图分类号: 

• TP332