摘要： 随着集成电路工艺进入深亚微米阶段后,电路复杂度的不断提高,特别是片上系统的不断发展,主要包括验证测试和制造测试的芯片测试,正在面临着巨大的挑战,传统的使用自动测试设备的测试方法越来越不能满足测试需要。各种用于提高芯片可测试性的可测性设计方法被提出,其中逻辑内建自测试方法已经被证明为大规模集成电路(VLSI)和SOC测试的一项有效的可测试性设计方法。文章首先对Logic BIST的基本原理结构进行介绍,然后对其在实践应用中的一些难点问题进行详细分析,最后给出针对一款高性能通用处理器实验的结果。

关键词: 可测性设计, 逻辑内建自测试, 测试点插入

Abstract: When the process of very large-scale integrated circuits(VLSI) scales down into deep sub-micron,the complexity of circuit designs has greatly increased.Test of a chip,including validation test and manufacturing test,has posed some new challenges,especially with the emergence of system-on-chip(SOC).Traditional test methods based on the automatic test equipment(ATE) are becoming more and more unacceptable.Logic built-in self-test(Logic BIST) has been widely accepted as an effective DFT technique for VLSI and SOC designs,among many kinds of proposed design for testability(DFT) techniques to improve testability of chip.The basic theoretical structure of logic BIST is firstly introduced.Then some important and complicated issues of logic BIST application are discussed.Finally,the paper shows some experimental results of logic BIST implementation on a high-performance general-purposed CPU design.

中图分类号: 

• TN405