计算机工程 ›› 2019, Vol. 45 ›› Issue (4): 72-77.doi: 10.19678/j.issn.1000-3428.0049763

• 移动互联与通信技术 • 上一篇    下一篇

并行高吞吐率多模极化码编码器设计

刘丽华1,2,管武1,梁利平1   

  1. 1.中国科学院微电子研究所,北京 100029; 2.中国科学院大学,北京 100029
  • 收稿日期:2017-12-20 出版日期:2019-04-15 发布日期:2019-04-15
  • 作者简介:刘丽华(1993—),女,硕士研究生,主研方向为通信与信息处理;管武,副研究员;梁利平,研究员
  • 基金项目:

    国家自然科学基金面上项目(61471354)

Design of Parallel High Throughput Multi-mode Polar Codes Encoder

LIU Lihua 1,2,GUAN Wu 1,LIANG Liping 1   

  1. 1.Institute of Microelectronics of the Chinese Academy of Sciences,Beijing 100029,China; 2.University of Chinese Academy of Sciences,Beijing 100029,China
  • Received:2017-12-20 Online:2019-04-15 Published:2019-04-15

摘要:

为获得可以支持多种码长、具有更高吞吐率的极化码编码器,提出一种32 bit并行级联的多模极化码编码器结构。每时钟周期内更新生成矩阵的32行,进行32 bit并行编码,从而加快编码速度。通过两级编码结构的级联简化编码器结构,以支持64 bit~4 096 bit码长的极化码编码。实验结果表明,在Xilinx XC6VLX240t的FPGA上,该编码器主频为303.82 MHz,吞吐率为9.72 Gb/s,寄存器与查找表资源相比快速傅里叶变换结构分别降低了77.6%与63.3%,在65 nm CMOS工艺下主频可达0.796 GHz,吞吐率可达24.615 Gb/s。

关键词: 极化码编码器, 高吞吐率, 并行, 多模, ASIC实现

Abstract:

A 32 bit parallel concatenated multi-mode polar codes encoder structure is proposed to obtain a polar codes encoder which support multiple codes lengths and have higher throughput.32 rows of the generated matrix are updated in each clock cycle,and 32 bit parallel coding is performed to speed up the coding.The structure of the encoder is simplified by a cascade of two-level coding structures to support 64 bit to 4 096 bit polarization coding.Experimental results show that on Xilinx XC6VLX240t FPGA,the main frequency of the proposed encoder is 303.82 MHz and the throughput is 9.72 Gb/s,compared with Fast Fourier Transform(FFT) structure,its register and lookup table resources are 77.6% and 63.3% lower,respectively,the main frequency can reach 0.796 GHz and the throughput can reach 24.615 Gb/s under 65 nm CMOS process.

Key words: polar codes encoder, high throughput, parallel, multi-mode, ASIC implementation

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