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计算机工程 ›› 2012, Vol. 38 ›› Issue (18): 231-233.doi: 10.3969/j.issn.1000-3428.2012.18.062

• 工程应用技术与实现 • 上一篇    下一篇

基于FPGA的多模式匹配算法研究与实现

骆 潇1，郭 健1，邓 敏1，白 斌2   

  1. (1. 西南电子电信技术研究所，成都 610041；2. 中国电子科技集团公司第30研究所，成都 610000)
  • 收稿日期:2011-11-14 修回日期:2012-01-14 出版日期:2012-09-20 发布日期:2012-09-18
  • 作者简介:骆 潇(1980－)，女，工程师，主研方向：光纤网络通信，高速网络数据处理；郭 健、邓 敏、白 斌，工程师
  • 基金项目:
    教育部人文社科基金资助项目(10YJCZH169)；四川省金融智能与金融工程重点实验室基金资助项目(FIFE2010-P05)

Research and Realization of Multiple Patterns Matching Algorithm Based on FPGA

LUO Xiao 1, GUO Jian 1, DENG Min 1, BAI Bin 2   

  1. (1. Southwest Electronics and Telecommunication Technology Research Institute, Chengdu 610041, China; 2. The 30th Institute of China Electronics Technology Group Corporation, Chengdu 610000, China)
  • Received:2011-11-14 Revised:2012-01-14 Online:2012-09-20 Published:2012-09-18

PDF

754

被引次数

4

摘要： 针对模式匹配软件算法速度慢、正确率低等问题，提出一种基于FPGA的硬件多模式匹配算法，通过设计窗口折叠的布鲁姆过滤器，有效减小资源消耗。与多级确认机制结合可降低虚警率，并采用不同于传统方式的并行结构提高查询速度，实现高效率无虚警的精确模式匹配。实验结果表明，采用该算法的高速入侵检测系统吞吐率可达到10 Gb/s。

关键词: 布鲁姆过滤器, 入侵检测, 模式匹配, 现场可编程门阵列, 流水线结构

Abstract: In view of the low efficiency of software performance in multi-pattern matching algorithm, a new hardware-based solution based on Field Programmable Gate Array(FPGA) is proposed. By using Bloom Filter(BF) data window collapsing, the on-chip hardware resource consumption is reduced and efficiency is improved. To reduce the possibility of false positive, the multilevel-verification is applied. A pipeline parallel structure is used to improve the query efficiency, which makes the pattern matching work in the high performance with no false positive. The method is applied in a high-speed network intrusion detection system. Experimental result shows that the throughout of system can reach the line speed of 10 Gb/s.

Key words: Bloom Filter(BF), intrusion detection, pattern matching, Field Programmable Gate Array(FPGA), pipeline structure

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