摘要： 为能够在现场可编程门阵列(FPGA)硬件平台上实现高速高质的图像缩放，提出一种基于FPGA的边缘自适应图像缩放算法。在非边缘区域采用双线性插值算法，在边缘区域使用具有方向性的改进三次插值算法，设计算法的硬件结构和运算逻辑结构，并用Verilog语言进行描述，给出目标代码。实验结果表明，该算法可以获得边缘清晰的缩放图像，且算法的复杂度低，放大2.5倍后图像的峰值信噪比为40.76 dB。

关键词: 图像缩放, 边缘相关度, 边缘方向角, 现场可编程门阵列, 峰值信噪比, 双线性插值

Abstract: In order to achieve high speed and high quality image scaling in Field Programmable Gate Array(FPGA), this paper proposes an edge adaptive image scaling algorithm based on FPGA. This algorithm uses bilinear interpolation algorithm out of the edge area, uses directional three interpolation algorithm in the edge area, designs the hardware structure and operation logic structure, uses Verilog language to describe, and gives the object code. Experimental results show that this algorithm can gain edge clear scaling image, the complexity of the algorithm is low, after magnifing 2.5 times, the Peak Signal to Noise Ratio(PSNR) of image is 40.76 dB.

Key words: image scaling, edge correlation, edge direction angle, Field Programmable Gate Array(FPGA), Peak Signal to Noise Ratio(PSNR), bilinear interpolation

中图分类号: 

• TP301.6