摘要： 在数字电路设计中,采用逻辑综合工具(如)完成硬件设计流图向门级结构描述的转换。综合出来的网EDADesign compileVerilog表将作为版图综合的输入数据。在此之前,需要对门级的网表进行模拟验证。在门级电路的仿真方面,一直有着优势。该文编VerilogHspice写了一个软件,旨在将门级的网表转化为相应的网表,以便于用来验证电路是否能实现预期的功能。VerilogHspiceStarsim

关键词: Verilog, Hspice, 网表, 单元库

Abstract: Gate_level netlists need to be verified before being put into layout . Hspice has its advantages in verifying them. Most netlists are verilog codes. A program is thus designed in order to transform a Verilog netlist to a Hspice netlist. The experimental results generated by LVS shows that this program works well.

中图分类号: 

• TP311.52