参考文献
[1]YU Zhiyi,YOU Kaidi,XIAO Ruijin,et al.An 800 MHz 320 mW 16-core Processor with Message-passing and Shared-memory Inter-core Communication Mechanisms[C]//Proceedings of IEEE International Solid-State Circuits Conference.Washington D.C.,USA:IEEE Press,2012:64-66.
[2]OU Peng,ZHANG Jiajie,QUAN Heng,et al.A 65 nm 39GOPS/W 24-core Processor with 11Tb/s/W Packet-controlled Circuit-switched Double-layer Network-on-chip and Heterogeneous Execution Array[C]//Pro-ceedings of IEEE International Solid-State Circuits Con-ference.Washington D.C.,USA:IEEE Press,2013:1-8.
(下转第59页)
(上接第54页)
[3]HU J,MARCULESCU R.Energy/Performance-aware Mapping for Regular NoC Architectures[J].IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems,2005,24(4):551-562.
[4]MURALI S,de MICHELI G.Bandwidth-constrained Mapping of Cores onto NoC Architectures[C]//Proceedings of Design,Automation and Test in Europe Conference and Exhibition.Washington D.C.,USA:IEEE Computer Society Press,2004:1-6.
[5]CHEN Guangyu,LI Feihui,SON S W,et al.Application Mapping for Chip Multiprocessors[C]//Proceedings of Design Automation Conference.New York,USA:ACM Press,2008:620-625.
[6]LIN L Y,WANG C Y,HUANG P J,et al.Com-munication-driven Task Binding for Multiprocessor with Latency Insensitive Network-on-chip[C]//Proceedings of Asia and South Pacific Design Automation Con-ference.New York,USA:ACM Press,2005:39-44.
[7]KANDEMIR M,OZTURK O,MURALIDHARA S P.Dynamic Thread and Data Mapping for NoC Based CMPs[C]//Proceedings of Design Automation Con-ference.New York,USA:ACM Press,2009:852-857.
[8]MANOLACHE S,ELES P,PENG Z.Fault and Energy-aware Communication Mapping with Guaranteed Latency for Applications Implemented on NoC[C]//Proceedings of Design Automation Conference.New York,USA:ACM Press,2005:266-269.
[9]YU Zhiyi,XIAO Ruijin,YOU Kaidi,et al.A 16-Core Processor with Shared-Memory and Message-Passing Communications[J].IEEE Transactions on Circuits and Systems I:Regular Papers,2014,61(4):1081-1094.
[10]程爱莲,潘赟,严晓浪.基于竞争概率的片上网络带宽分配方法[J].计算机工程,2012,38(22):55-58.
[11]全励,潘赟,丁勇,等.基于双维序路由策略的低能耗NoC网络分配[J].计算机工程,2012,38(13):13-16,21.
[12]尤凯迪,肖瑞瑾,权衡,等.适用于多核处理器的簇状片上网络设计[J].计算机工程,2011,37(21):211-213.
[13]LOIOLA E M,de ABREU N M M,BOAVENTURA-NETTO P O,et al.A Survey for the Quadratic Assignment Problem[J].European Journal of Opera-tional Research,2007,176(2):657-690.
[14]DICK R P,RHODES D L,WOLF W.TGFF:Task Graphs for Free[C]//Proceedings of International Conference on Hardware Software Codesign.Washington D.C.,USA:IEEE Computer Society Press,1998:97-105.
[15]COLE R.Parallel Merge Sort[J].SIAM Journal on Computing,1988,17(4):770-785.
[16]SAHU P K,CHATTOPADHYAY S.A Survey on Application Mapping Strategies for Network-on-chip Design[J].Journal of Systems Architecture,2013,59(1):60-76.
编辑陆燕菲 |