基于可控制性度量的图神经网络门级硬件木马检测方法

doi:10.19678/j.issn.1000-3428.0068248

摘要/Abstract

摘要：

随着全球化的不断深入, 第三方知识产权(IP)核应用越来越广泛。随着硬件木马攻击技术逐渐成熟, 使得在芯片设计阶段植入硬件木马成为可能。因此, 在芯片设计过程中面临IP核被植入木马的严重威胁, 现有研究所提的硬件木马检测方法具有依赖黄金参考电路、需要完备的测试向量、大量的样本进行学习等特征。面向IP核的硬件木马检测需求, 提出一种基于可控制性度量的图神经网络检测方法。该方法以门级网表作为输入, 首先以可控制性值为指导, 得到可疑的门节点, 用于缩小搜索范围; 然后利用可疑门节点生成对应的子图, 利用图卷积神经网络从子图中提取特征, 实现对子图的分类和检测, 最终识别硬件木马。实验结果表明, 该方法无须测试激励和黄金模型, 利用硬件木马的隐蔽特性与结构特征相结合的方法提升硬件木马的检测准确率, 平均真阳率为100%, 假阳率为0.75%, 在保证较高真阳率的同时可有效降低假阳率, 达到较好的检测效果。

关键词: 知识产权核, 硬件木马, 可控制性度量, 子图, 图卷积神经网络

Abstract:

With the continuous increase in globalization, third-party Intellectual Property (IP) core applications have become increasingly widespread. The gradual maturity of hardware Trojan attack technology enables the implantation of hardware Trojan in the chip design process, posing a serious threat to chip design security. Hardware Trojan detection methods proposed in the current study have the following drawbacks: they rely on golden reference circuits, require complete test patterns, and require a large number of samples for learning. This study proposes a graph neural network detection method based on controllability metrics for the hardware Trojan detection requirements of IP cores. This method uses a gate-level netlist as the input and first uses controllability values as guidance to obtain suspicious gate nodes to narrow the search range. Subsequently, the suspicious gate nodes are generated into corresponding subgraphs, and the graph convolutional neural network is used to extract features from the subgraphs. Thus, it detects the subgraphs and ultimately identifies the existence of hardware Trojans. The experimental results demonstrate that the proposed method does not require testing patterns and golden models. By combining the hidden characteristics and structural features of hardware Trojans, the detection accuracy is improved. The average True Positive Rate(TPR) and False Positive Rate(FPR) are 100% and 0.75%, respectively. Additionally, it effectively reduces the FPR and achieve satisfactory detection results while ensuring a high TPR.

Key words: Intellectual Property(IP) core, hardware Trojan, controllability metric, subgraph, graph convolutional neural network

张洋, 刘畅, 李少青. 基于可控制性度量的图神经网络门级硬件木马检测方法[J]. 计算机工程, 2024, 50(7): 164-173.

Yang ZHANG, Chang LIU, Shaoqing LI. Gate-Level Hardware Trojan Detection Method for Graph Neural Networks Based on Controllability Metrics[J]. Computer Engineering, 2024, 50(7): 164-173.

https://www.ecice06.com/CN/Y2024/V50/I7/164

图/表 12

图1 电路中木马部分与正常部分分布

Fig.1 Distribution of Trojans and normals parts in the circuit

图2 RS232-T1000的硬件木马结构

Fig.2 Hardware Trojan structure of RS232-T1000

图3 硬件木马检测总体流程

Fig.3 The overall procedure of hardware Trojan detection

图4 隐蔽性计算示例

Fig.4 An example of concealment calculation

图5 子图示意图

Fig.5 Schematic diagram of subgraph

图6 硬件木马结构示意图

Fig.6 Schematic diagram of hardware Trojan structure

图7 隐蔽性度量结果

Fig.7 Results of the concealment metric

图8 子图的节点数对收敛速度的影响

Fig.8 The impact of the node number of a subgraph on convergence speed

图9 检测出的硬件木马子图示例

Fig.9 Example of a detected hardware Trojan subgraph

图10 检测出的正常子图示例

Fig.10 Example of a detected normal subgraph

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