Abstract: Aiming to the specific application environment of embedded processors, this paper gives a hybrid mechanism which combines custom-designed Branch Target Buffer(BTB) with improved neural network arithmetic for the dynamic branch prediction. In this mechanism, neural network arithmetic implements an approach of global indexing with less resource rather than the normal indexing way based on the instruction address. In use of the unique feature of embedded applications, the BTB structure makes accurate prediction for the final branch instruction in the loop logic. The result indicates that this mechanism achieves high precision with lower complexity.
hybrid branch prediction,
Branch Target Buffer(BTB),