Abstract: This paper proposes a simple frequent value and frequent pattern based compression method, and a chip-multiprocessor design combining cache compression and interface compression techniques. The full system simulation shows that Cache compression and interface compression techniques can increase the effective Cache capacity and effective pin bandwidth, and then improve the performance of system. Experimental results show that only using cache compression can improve performance by 10%, only using interface compression can improve performance by 5.5%, combining cache compression and link compression techniques can improve performance by 12%.

Key words: chip multiprocessor, cache compression, interface compression

摘要： 提出一种简单的基于频繁值和频繁模式的压缩方法，给出结合Cache压缩技术和接口压缩技术的片上多处理器结构。全系统的模拟结果表明Cache压缩技术和接口压缩技术能提高片上多处理器中Cache的有效容量和pin的有效带宽，从而提高系统的性能。实验表明只采用Cache压缩技术平均能提高10%的性能，只采用接口压缩技术平均能提高5.5%的性能，同时采用Cache压缩技术和接口压缩技术平均能提高12%的性能。

关键词: 片上多处理器, Cache压缩, 接口压缩

CLC Number: 

• TP391