Abstract: A novel DPC structure based on FPGA technology is proposed, which is based on decimation-in-time parallel radix-4 FFT algorithms. This paper develops the universal radix 4 butterfly which can be used in the three stages while doing the DPC. It can increase the usage of hardware resource. A parallel memory accessing for this DPC algorithm is used, which is based on “in-place” principle and allows conflict-free access to the 4 operands needed for calculation of the universal radix 4 butterfly in one clock. Block floating point algorithm is adopted which has the merits of high speed of fixed point and high accuracy of floating point. Results show that it computes a complex 4 096 point DPC within 140 μs.

Key words: Digital Pulse Compression(DPC), Fast Fourier Transform(FFT), butterfly

摘要： 研究一种基于现场可编程门阵列实现的高速脉冲压缩处理的硬件结构。设计通用的蝶形处理单元，使其在脉冲压缩处理的3个阶段都能使用，实现了硬件的共享，提高了硬件资源的利用效率。通过可使用原位运算的并行存储器结构，使得每个时钟周期均可完成一次蝶形运算，极大地提高了处理速度。采用块浮点处理单元，兼顾定点的高速率和浮点的高精度。经过实践验证，时钟在100 MHz时完成4 096点的脉冲压缩的时间为140 μs。

关键词: 数字脉冲压缩, 快速傅里叶变换, 蝶形单元

CLC Number: 

• TN79