摘要： 提出一种应用于NAND Flash控制器的并行BCH编/译码器，在译码阶段引入流水线操作和分组预取译码操作，提升BCH码的译码效率。实验结果表明，在NAND Flash的2 KB页读取操作中，该编/译码器纠正8 bit的随机错误只需要565个周期的译码时间，是采用按页预取译码方式所需时间的1/4。
关键词:
BCH码,
并行,
流水线,
NAND Flash控制器,
分组预取译码
Abstract: A new architecture of parallel BCH encoder and decoder applied in NAND Flash Controller is proposed. In order to obviously increase the throughput of decoder, pipeline operation and prefetch decoding in group operation are applied in the design. It takes 565 cycles to correct 8 bit random error after NAND Flash’s 2 KB page read operation, which is a quarter of the time cost by prefetch & decode in page.
Key words:
BCH code,
parallel,
pipeline,
NAND Flash controller,
prefetch decoding in group
中图分类号:
王杰, 沈海斌. NAND Flash控制器的BCH编/译码器设计[J]. 计算机工程, 2010, 36(16): 222-225.
WANG Jie, CHEN Hai-Bin. Design of BCH Encoder/Decoder for NAND Flash Controller[J]. Computer Engineering, 2010, 36(16): 222-225.