Abstract: This paper introduces a high-speed DDR SDRAM controller for video decoder SoC. DDR control unit and system local bus arbitrate unit are merged in one controller harmoniously. According to the requirement of the whole system and the characteristic of DDR SDRAM, the paper presents the optimized solution in structure and timing aspect. And it also presents the strategy of FPGA prototype verification and the implementation result on FPGA & ASIC.

Key words: Double data rate；Synchronous dynamic RAM；Video decoder；H.264；System on a chip(SoC)

摘要： 介绍了高速DDR SDRAM 控制器设计以及在视频解码芯片系统中的应用。该设计将DDR 控制单元和系统内部总线仲裁单元较好地整合成统一的控制器。根据DDR 的工作原理和系统带宽要求，给出了DDR 控制器关键部分在结构上和时序上的优化方案。同时还给出了FPGA 原型验证的策略以及最后FPGA 和ASIC 的实现结果。

关键词: DDR；SDRAM；视频解码芯片；H.264；片上系统