Abstract:
The forwarding engine of terabit router is designed and implemented. The module adopts parallel forwarding structure based on sub-module processor and parallel pipelining based on FPGA. The subsection routing lookup algorithms is used.They satisfy IPv6 and IPv4/IPv6 dual-stack core routers’ OC-192 (10Gbps) interfaces’ wire-speed forwarding. Analysis and experiment prove that the performance of the forwarding engine can reach the design aim effectively and satisfy the whole demands of terabit router
Key words:
router; Forwarding engine; FPGA; Parallel pipeline
摘要： 设计并实现了T 比特路由器中的转发引擎模块，该模块采用基于子模块处理器的并行转发结构，基于FPGA 的并行流水线处理技术，结合分段查表算法，实现了10GPOS 接口，IPv4/v6 双协议栈的线速转发。试验测试表明该引擎能高效、稳定地达到设计目标，充分满足T 比特路由器的整体需求
关键词:
比特路由器；转发引擎；FPGA；并行流水线
BIAN Yulan , WANG Yaoqing , ZHANG Bingyi , LI Yufeng , LAN Julong. Design and Implementation of High-speed Forwarding Engine in Terabit Router[J]. Computer Engineering, 2006, 32(3): 251-253.
边裕兰，王耀青，张冰怡，李玉峰，兰巨龙. T 比特路由器高速转发引擎的设计与实现[J]. 计算机工程, 2006, 32(3): 251-253.