Abstract: A pipelined splittable multiply-accumulate unit architecture designed for media digital signal processor is presented in this paper. The MAC operations are pipelined to achieve single-cycle 32-bit × 32-bit MAC throughput at 200 MHz. Splittable data-path architecture is employed to support 4-way 16-bit × 16-bit single-instruction-multiple-data (SIMD) MAC instructions. The MAC architecture is physically verified in silicon DSP chip.

Key words: Multiply-accumulate (MAC); SIMD; Pipelined; Splittable

摘要： 乘加器是媒体数字信号处理器的关键运算部件。该文结合32 位数字信号处理器芯片MD32 开发(“863”计划)实践，提出了一种流水化可拆分的乘加器硬件实现结构，通过对乘法操作的流水处理实现了200MHz 工作频率下的单周期吞吐量指标，通过构造可拆分的数据通道实现了对SIMD 乘法指令的支持，支持4 个通道16 位媒体数据的并行乘法，大大提升了处理器的媒体处理性能。文中对所提出的乘加器体系结构，给出了理论依据和实验结果，通过MD32 的流片实现得到了物理验证。

关键词: 乘加器；SIMD；流水化；可拆分