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Computer Engineering ›› 2006, Vol. 32 ›› Issue (8): 252-254.

• Engineer Application Technology and Realization • Previous Articles     Next Articles

The FPGA Design of Large Scale Array Signal Processor

JIANG Peng1, HE Guojian1, CAI Huizhi1, JI Xiaoyan2   

  1. 1. Acoustic Institute of CAS, Beijing 100080; 2. 717 Institute of CSIC, Wuhan 430074
  • Online:2006-04-20 Published:2006-04-20

大规模阵列信号处理机的 FPGA 设计

江 鹏 1,何国建1,蔡惠智1,季晓燕2   

  1. 1. 中国科学院声学研究所,北京 100080;2. 中船重工717 研究所,武汉 430074

Abstract: In the modern communication, sonar and radar systems, it needs to process huge data. One of the effective ways to solve this problem is to build a system with multiprocessor, so it can enhance the processing ability. According to the demands of the system, this paper designs a high speed array signal processing board which is based on CPCI structure. It chooses the TigerSharc101 as the core processor, the peak processing ability of the board is 14.4GFLOPS. The board has link ports to realize the communication between TS101 and boards. This paper introduces the base structure of the board and FPGA design and emphasizes on the host interface design. These applications show that the board has a great processing ability and expansibility.

Key words: CPCI bus; Array signal processing; TigerSharc101

摘要: 在雷达和声纳系统中,需要进行非常复杂的数据处理。目前解决这些问题的有效办法是将多个DSP 组成阵列处理系统,以增加整体数据处理能力。针对系统的要求,采用基于CPCI 的高速阵列信号处理板卡。该板选用AD 公司的高性能浮点DSP 处理器TigerSharc101,使整板具有14.4GFLOPS 的峰值浮点运算能力,它提供Link Port 来实现片间和板间通信。该文介绍了该板的原理框图,FPGA 的实现结构,着重于Host 接口逻辑设计。实践证明,该板具有了超强的运算能力,良好的扩展性。

关键词: CPCI 总线;阵列信号处理;TigerSharc101