Abstract: This paper discusses the theory of AES algorithm, and describes its process and structure with Verilog HDL. Based on the structure, it completes the FPGA design of AES encryption and decryption algorithm when block length is 128bits. When the system clock frequency is 25MHz,the encryption speed of the design is 3Gbits/s which reaches the top level in the world

Key words: AES; FPGA; Rijndael algorithm; Hardware design; Pipeline

摘要： 分析了高级加密标准算法（AES）的原理，并在此基础上对AES 的硬件实现方法进行研究，用硬件设计语言（Verilog HDL）描述了该算法的基本过程和结构，完成了分组长度为128 比特的AES 加/解密芯片设计。仿真结果表明，在时钟频率为25MHz 前提下，加/解密速度达3Gbit/sec，处理速度达到世界领先水平。

关键词: AES；FPGA；Rijndael 算法；硬件设计；流水线。