Abstract: This paper proposes a novel efficient area reduction solution for hardware implementation of the advanced encryption standard (AES) algorithm which works in SSX11-140 secure processor architecture. It presents an optimization design in subkeys saving and MixColumns/InvMixColumns operations; The key expansion and the encryption/decryption implementations share the key components such as S-BOX and mix columns. The experiment result shows that the design can satisfy the requirements of the factual application, in the same time it can reduce the area cost effectively, and can be applied in smart architectures.

Key words: Advanced encryption standard(AES), Rijndael, Efficient area reduction, Hardware implementation

摘要： 给出了在一种安全处理器(SSX11-140)中有效缩减AES算法硬件实现面积的设计方案。该方案对轮密钥存储、列混合变换及其逆变换等操作进行了优化处理，并在密钥扩展、加密计算及解密计算中对S-盒、列混合变换等关键计算部件进行了复用。实验结果表明，该设计在满足实际应用性能需求的同时，有效地减小了硬件实现面积，可应用于小规模体系结构中。

关键词: 高级数据加密标准, Rijndael, 面积有效缩减, 硬件实现