Abstract: The RAID50 model of multi-controller stripe and the two-level address mapped mode of the host virtual volume address to high array and low array stripe is designed for enhancing I/O access concurrency. The transmission efficiency between the Cache memory and storage media is improved by using extend block that consists of sequential I/O multi-block and equals with Cache page size as RAID50 transmission granularity. The hash link lookup algorithms on Cache descriptor block and the second chance replacement algorithms on Cache page access frequency count are designed. The concurrent policy of the host data receiving and storage device pre-reading is implemented. The results show that the design improves effectively the storage system I/O performance.

Key words: RAID50, Cache, High array, Low array, Adapter stripe

摘要： 设计了一种多个控制卡分条的RAID50模型和主机虚拟卷地址到所属高级别阵列、低级别阵列分条的二级地址映射模式，以提高I/O访问的并发性。定义多个连续I/O块为扩展块并等同于Cache页大小，且作为RAID50传输粒度，进一步改善内存与存储设备之间的传输效率。设计了基于Cache描述符控制块的哈希链式查找算法和基于Cache页访问频率计数的二次机会置换算法，实现了一种主机数据接收与RAID50存储设备预读并发进行的策略。结果表明，该设计有效地提高了存储系统的I/O性能。

关键词: 控制卡分条的分布式冗余校验磁盘阵列, 高速缓存, 高级别阵列, 低级别阵列, 控制卡分条