Abstract: A novel FPGA implementation of the secure hash algorithm 512 (SHA-512) is proposed. The proposed architecture exploits the benefits of parallel computer through pre-computation of intermediate temporal values. Parallel computer is based on the decomposition of the SHA-512 expression to separate information dependencies and independencies. This allows pre-computation of intermediate temporal values in parallel to the calculation of other independent values. The implementation’s characteristics are compared to alternative implementations proposed by the academia and the industry, which are available in the international IP market. The proposed implementation achieves a throughput that exceeds 1 652Mbit/s, which is the highest among MD-5 and SHA-1 IP core for the targeted XILINX technology.

Key words: Hash function, SHA-1, SHA-512

摘要： 在分析NIST的散列函数SHA-512基础上，对散列函数SHA-512中的关键运算部分进行了分解，通过采用中间变量进行预行计算，达到了SHA-512中迭代部分的并行计算处理，提高了运算速度。通过这种新的硬件结构，优化后的散列函数SHA-512在71.5MHz时钟频率下性能达到了1 652Mbit/s的数据吞吐量，比优化前性能提高了约2倍，最后还将实验结果与MD-5、SHA-1商用IP核性能进行了比较。

关键词: 单向散列函数, SHA-1, SHA-512