Abstract: This paper proposes hardware implementation architecture for deblocking loop filter in a multi-mode video decoder chip which supports H.264/AVC and AVS. This architecture adopts appropriate management of buffer-on-chip and pipelining design to improve filter speed and efficiency. The reuse with two standards can save area efficiently.

Key words: H.264/AVC, AVS, Reuse, Deblocking loop filter, Pipeline design

摘要： 提出了一种支持H.264/AVC和AVS两款视频编解码标准的解码芯片中去块效应环路滤波(Deblocking Loop Filter)的硬件实现结构。这种结构通过采用恰当的片内Buffer管理方式和流水线设计，解决了环路滤波的硬件实现时速度慢的问题，使得效率提高。通过标准的复用，能有效地节省面积。

关键词: H.264/AVC, AVS, 复用, 去块效应环路滤波, 流水线设计

CLC Number: 

• TN919