Abstract:

10-gigabit Ethernet MAC uses 64bits data path and 156.25MHz frequency to meet the bandwidth of 10Gb/s. The wider data path and the higher frequency bring new challenges to the implementation of 10-gigabit Ethernet MAC controller. These challenges include getting data boundary, CRC encode/check, high frequency logic design and compliant with 1-gigabit Ethernet. This paper proposes some solutions, which are auxiliary counter, cross pipeline CRC, deep pipeline and asynchrony RAM. It also designs a 10-gigabit Ethernet MAC controller by using these solutions. The post place and route simulation result of this controller indicates these solutions are correct and feasible.

Key words: 10-gigabit Ethernet, MAC, XGMII, CRC, post place and route simulation

摘要： 为了与10Gb/s的带宽相匹配，万兆以太网MAC层内部采用64位数据宽度，156.25MHz的工作频率。数据宽度的加宽和频率的提高给万兆以太网MAC层控制器的实现带来了新的挑战。这些挑战表现在数据域边界获取，CRC编码/校验，高频电路设计以及与千兆以太网兼容等方面。文章提出了使用辅助计数、交叉流水CRC、细化流水级和异步RAM等方案来解决这些问题，并采用上述解决方案设计实现了万兆以太网MAC层控制器。对控制器进行后时序仿真的结果证实了方案的正确性和可行性。

关键词: 万兆以太网, MAC, XGMII, CRC, 后时序仿真

CLC Number: 

• TP393.02