Abstract: On the basis of USB transport protocol research, this paper establishes the mathematical model of data sampling and presents a design method of digital phase locked logic(DPLL) which is simple and reliable. In the given cycle difference range of USB host and device, the USB device controller transmits accurately. On the basis of band utility, this paper proposes the buffer implementation scheme. The USB device controller is embedded in the SoC chip based on Godson CPU and is validated by Field Programmable Gate Array(FPGA).

Key words: Universal Serial Bus(USB), Digital Phase Locked Logic(DPLL), dual-port RAM

摘要： 在研究通用串行总线(USB)协议的基础上，建立了数据采样的数学模型，并基于该数学模型提出了数字锁相环的一种简单可靠的实现方法。在给定的USB主机和设备周期差异范围内，该USB设备能够正确传输。在保证带宽利用率的基础上，设计了缓冲区的实现方案，并将该USB设备控制器应用在基于龙芯的SoC芯片上，用FPGA进行了验证。

关键词: 通用串行总线(USB), 数字锁相环, 双端口RAM

CLC Number: 

• TP334