Abstract: This paper presents a solution of a high speed, low-cost and reconstructable encryption engine based on the AES encryption aiming to solve the balance problem of hardware resources and circuit performance in commercial encryption engines. According to FPGA inherent structural features, the four-level pipeline structure is improved and the encryption module is described with VHDL. By expanding the password encryption engine, the goal of real-time, reconstructability and security is achieved. Compared with some other encryption engines, this encryption engine has a good safety performance guarantee, speed and resources performance ratio.

Key words: reconstructable, VHDL, encryption engine

摘要： 针对商业加密引擎中硬件资源和电路性能平衡问题，提出一种基于AES的低成本可重构的高速加密引擎的设计方案。该方案在AES加密算法的基础上，根据FPGA内在的结构特点，利用VHDL语言对其加密模块进行描述，改善4级流水线结构，结合密码库的扩展设计，使系统达到实时重构安全策略的目的。通过对高速加密引擎的加密模块的实验仿真结果分析和总体性能评估，证明了该加密引擎不仅具有良好的安全性能，而且在速度和资源性能比方面有优势。

关键词: 可重构, VHDL语言, 加密引擎

CLC Number: 

• TP309