Abstract: This paper analyzes the basic principle of the AES algorithm, and presents a hardware implementation structure based on FPGA. The principle description and hardware implementation structure of data encryption modules and key expansion modules are presented. In the structure, the core computing module reuse design idea is joined which can reduce the use of chip resources without impacting system efficiency. The chip-level test of the system shows the system processing speed can reach 405 Mb/s based on the clock frequency of 38 MHz.

Key words: Advanced Encryption Standard(AES), block cipher, encryption

摘要： 分析AES算法原理，构建基于FPGA的硬件实现框架，描述数据加解密单元和密钥扩展单元的工作机制和硬件结构，引入核心运算模块复用的设计思想，在不影响系统效率的前提下降低芯片资源的使用率，并对该系统结构进行了芯片级的验证。实验结果表明，在38 MHz工作频率下，该系统的处理速度为405 Mb/s。

关键词: 高级加密标准, 分组密码, 加密

CLC Number: 

• TP309