Abstract: A design scheme of a CPU simulator which is compatible with MIPS32 instruction set is presented. It simulates hardware behavior of CPU by using C language, and it can implement all the MIPS32 instructions excluding floating-point instruction, such as parameterize main memory, unifies 2-way set associative instruction and data cache, embeding reconfigurable branch predictor and ELF interpreter. An application example is given.

Key words: MIPS processor, simulator, cache, branch prediction

摘要： 描述一个与MIPS32指令集兼容的CPU模拟器设计方案，该方案用C语言描述处理器的硬件行为，模拟CPU指令的执行过程，实现MIPS32除浮点运算指令以外的所有指令，有大小可配的主存储器、指令和数据统一的二相关高速缓存Cache，内置类型可配的分支预测器和ELF文件解析器，并给出设计的应用实例。

关键词: MIPS处理器, 模拟器, 高速缓存, 分支预测

CLC Number: 

• TP311