Abstract: In view of the requirement of Quality of Service(QoS) realization mechanism and strict dynamic priority arrangement, this paper introduces a kind of heap sort algorithm for FPGA realization easily in the exchange system design. The algorithm which unifies the modulation and the condition machine is used to produce the module design mentality, the emulator executes by using XilinxISE8.2i+ModerSim6.2, and the procedure downloads the experiment developping board to validate the system. The result indicates that the design has a high utilization rate of resources and a quick speed of operating. It is suitable for the realization of outstanding QoS mechanism in hardware.

Key words: heap sort, Quality of Service(QoS), FPGA, Verilog HDL language

摘要： 针对服务质量(QoS)的实现机制和严格动态优先级排序要求，在交换系统设计中引入一种易于FPGA实现的堆排序算法。采用模块化和状态机相结合的设计方法，给出模块的设计过程，利用XilinxISE8.2i＋ModerSim6.2软件对设计程序进行仿真，将程序下载到实验开发板上对系统进行验证，结果表明该设计的资源利用率高、运行速率快，适用于QoS机制的硬件实现。

关键词: 堆排序, 服务质量, 现场可编程门阵列, Verilog HDL语言

CLC Number: 

• TP393